Guest Integrity at Risk Due to Code Bug in Secure TSC

CVE-2023-31347

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Key Information

Vendor: Amd
Status: 3rd Gen Amd Epyc™ Processors; 4th Gen Amd Epyc™ Processors
Vendor: CVE Published:; 13 February 2024

Summary

Due to a code bug in Secure_TSC, SEV firmware may allow an attacker with high privileges to cause a guest to observe an incorrect TSC when Secure TSC is enabled potentially resulting in a loss of guest integrity.

Affected Version(s)

3rd Gen AMD EPYC™ Processors <= various

4th Gen AMD EPYC™ Processors <= various

Timeline

Vulnerability published.
Feb 13, 2024
Vulnerability Reserved.
Apr 27, 2023

Collectors

NVD DatabaseMitre Database